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general description the max1142/MAX1143 are 200ksps, 14-bit adcs. these serially interfaced adcs connect directly to spi?, qspi?, and microwire? devices without external logic. they combine an input scaling network, internal track/hold, a clock, +4.096v reference, and three general-purpose digital output pins (for external multiplexer or pga control) in a 20-pin ssop package. the excellent dynamic performance (sinad 3 81db), high-speed (200ksps), and low power (7.5ma) of these adcs, make them ideal for applications such as indus- trial process control, instrumentation, and medical applications. the max1142 accepts input signals of 0 to +12v (unipolar) or 12v (bipolar), while the MAX1143 accepts input signals of 0 to +4.096v (unipo- lar) or 4.096v (bipolar). operating from a single +4.75v to +5.25v analog supply and a +4.75v to +5.25v digital supply, power-down modes reduce cur- rent consumption to 1ma at 10ksps and further reduce supply current to less than 20a at slower data rates. a serial strobe output (sstrb) allows direct connection to the tms320-family of digital signal processors. the max1142/MAX1143 user can select either the internal clock, or an external serial-interface clock for the adc to perform analog-to-digital conversions. the max1142/MAX1143 feature internal calibration cir- cuitry to correct linearity and offset errors. on-demand calibration allows the user to optimize performance. three user-programmable logic outputs are provided for the control of an 8-channel mux or a pga. applications industrial process control industrial i/o modules data-acquisition systems medical instruments portable and battery-powered equipment features ? 200ksps (bipolar) and 150ksps (unipolar) sampling adc ? 14-bits, no missing codes ? 1lsb inl guaranteed ? 81db (min) sinad ? +5v single-supply operation ? low power operation, 7.5ma (unipolar mode) ? 2.5a shutdown mode ? software-configurable unipolar & bipolar input ranges 0 to +12v and 12v (max1142) 0 to +4.096v and 4.096v (MAX1143) internal or external reference ? internal or external clock ? spi/qspi/microwire-compatible wire serial interface ? three user-programmable logic outputs ? small 20-pin ssop package max1142/MAX1143 14-bit adc, 200ksps, +5v single-supply with reference ________________________________________________________________ maxim integrated products 1 top view cs shdn rst 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 agnd ain cref av dd agnd refadj ref din dv dd dgnd sclk p2 p1 p0 sstrb dgnd 12 11 9 10 dout max1142 MAX1143 ssop pin configuration 19-2037; rev 0; 5/01 ordering information part temp. range pin- package inl (lsb) max1142 acap 0 c to +70 c 20 ssop 1 max1142bcap 0 c to +70 c 20 ssop 2 functional diagram appears at end of data sheet. typical application circuit appears at end of data sheet. spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. ordering information continued at end of data sheet. for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxims website at www.maxim-ic.com.
max1142/MAX1143 14-bit adc, 200ksps, +5v single-supply with refer ence 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to agnd, dv dd to dgnd ............................. -0.3v to +6v agnd to dgnd ..................................................... -0.3v to +0.3v ain to agnd ..................................................................... 16.5v refadj, cref, ref to agnd ................. -0.3v to (av dd + 0.3v) digital inputs to dgnd ............................................. -0.3v to +6v digital outputs to dgnd ......................... -0.3v to (dv dd + 0.3v) continuous power dissipation (t a = +70 c) 20-ssop (derate 8.00mw/ c above +70 c) ............... 640mw operating temperature ranges max114_cap ...................................................... 0 c to +70 c max114_eap .................................................... -40 c to +85 c storage temperature range ............................. -60 c to +150 c junction temperature ...................................................... +150 c lead temperature (soldering, 10s) ................................. +300 c electrical characteristics (av dd = dv dd = +5v 5%, f sclk = 4.8mhz, external clock (50% duty cycle), 24 clocks/conversion (200ksps), bipolar input, external v ref = +4.096v, v refadj = av dd , c ref = 2.2 f, c cref = 1 f, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units dc accuracy (note 1) resolution 14 bits unipolar mode max114_a 1 relative accuracy (note 2) inl max114_b 2 lsb differential nonlinearity dnl unipolar mode 1 lsb transition noise 0.34 lsb rms unipolar 4 offset error bipolar 6 mv unipolar 0.2 gain error (note 3) bipolar 0.3 %fsr o f f s e t d r i f t ( b i p o l a r a n d u n i p o l a r ) excluding reference drift 1 ppm/ o c g a i n d r i f t ( b i p o l a r a n d u n i p o l a r ) excluding reference drift 1 ppm/ o c dynamic specifications (5khz sine-wave input, 200ksps, 4.8mhz clock, bipolar input mode). (max1142, 24vp-p. MAX1143, 8.192vp-p) f in = 5khz 81 sinad f in = 100khz 82 db f in = 5khz 82 snr f in = 100khz 82 db f in = 5khz -88 thd f in = 100khz 91 db f in = 5khz 90 sfdr f in = 100khz 95 db analog input unipolar 0 12 max1142 bipolar -12 12 unipolar 0 4.096 input range MAX1143 bipolar - 4 . 0 9 6 4.096 v
max1142/MAX1143 14-bit adc, 200ksps, +5v single-supply with refer ence _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = dv dd = +5v 5%, f sclk = 4.8mhz, external clock (50% duty cycle), 24 clocks/conversion (200ksps), bipolar input, external v ref = +4.096v, v refadj = av dd , c ref = 2.2 f, c cref = 1 f, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units unipolar 7.5 10.0 max1142 bipolar 5.9 7.9 unipolar 100 1000 input impedance MAX1143 bipolar 3.4 4.5 k w input capacitance 32 pf conversion rate internal clock frequency 4 mhz aperture delay t ad 10 ns aperture jitter t aj 50 ps mode 1 (24 external clock cycles per conversion) unipolar 0.1 3 external clock frequency f sclk bipolar 0.1 4.8 mhz unipolar 4.17 125 sample rate f s = f sclk /24 bipolar 4.17 200 ksps unipolar 8 240 conversion time (note 4) t conv+acq = 24 / f sclk bipolar 5 240 s mode 2 (internal clock mode) external clock frequency (data transfer only) 8 mhz conversion time sstrb low pulse width 4 6 s unipolar 1.82 acquisition time bipolar 1.14 s mode 3 (32 external clock cycles per conversion) external clock frequency f sclk unipolar or bipolar 0.1 4.8 mhz sample rate f s = f sclk /32 unipolar or bipolar 3.125 150 ksps conversion time (note 4) t conv+acq = 32 / f sclk unipolar or bipolar 6.67 320 s internal reference output voltage v ref 4.056 4.096 4.136 v ref short circuit current 24 ma output tempco 20 ppm/ o c capacitive bypass at ref 0.47 10 f maximum capacitive bypass at refadj 10 f refadj output voltage 4.096 v refadj input range for small adjustments from 4.096v 100 mv
max1142/MAX1143 14-bit adc, 200ksps, +5v single-supply with refer ence 4 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = dv dd = +5v 5%, f sclk = 4.8mhz, external clock (50% duty cycle), 24 clocks/conversion (200ksps), bipolar input, external v ref = +4.096v, v refadj = av dd , c ref = 2.2 f, c cref = 1 f, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units refadj buffer disable threshold to power-down the internal reference a v d d - 0 . 5 v a v d d - 0 . 1 v v buffer voltage gain 1 v/v external reference (reference buffer disabled. reference applied to ref) input range (notes 5 and 6) 3.0 4.096 4.2 v v ref = 4.096v, f sclk = 4.8mhz 250 v ref = 4.096v, f sclk = 0 230 input current in power-down, f sclk = 0 0.1 m a digital inputs input high voltage v ih 2.4 v input low voltage v il 0.8 v input leakage i in v in = 0 or dv dd 1 m a input hysteresis v hyst 0.2 v input capacitance c in 10 pf digital outputs output high voltage v oh i source = 0.5ma dv dd - 0.5 v i sink = 5ma 0.4 output low voltage v ol i sink = 16ma 0.8 v three-state leakage current i l cs = dv dd 10 m a three-state output capacitance cs = dv dd 10 pf power supplies analog supply (note 7) av dd 4.75 5 5.25 v digital supply (note 7) dv dd 4.75 5 5.25 v unipolar mode 5 8 bipolar mode 8.5 11 ma analog supply current i analog s h d n = 0 , o r s o f t w a r e p o w e r - d o w n m o d e 0.3 10 m a unipolar or bipolar mode 2.5 3.5 ma digital supply current i digital s h d n = 0 , o r s o f t w a r e p o w e r - d o w n m o d e 2.2 10 m a power supply rejection ratio (note 8) psrr av dd = dv dd = 4.75v to 5.25v, 72 db
max1142/MAX1143 14-bit adc, 200ksps, +5v single-supply with refer ence _______________________________________________________________________________________ 5 note 1: tested at av dd = dv dd = +5v, bipolar input mode. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset error have been nulled. note 3: offset nulled. note 4: conversion time is defined as the number of clock cycles multiplied by the clock period, clock has 50% duty cycle. includes the acquisition time. note 5: adc performance is limited by the converters noise floor, typically 300 vp-p. note 6 when an external reference has a different voltage than the specified typical value, the full scale of the adc will scale proportionally. note 7: electrical characteristics are guaranteed from av dd(min) = dv dd(min) to av dd(max) = dv dd(max) . for operations beyond this range, see the typical operating characteristics . for guaranteed specifications beyond the limits, contact the factory. note 8: defined as the change in positive full-scale caused by a 5% variation in the nominal supply voltage. timing characteristics (figures 5 and 6) (av dd = dv dd = +5v 5%, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max unit acquisition time t acq 1.14 m s din to sclk setup t ds 50 ns din to sclk hold t dh 0 ns sclk to dout valid t do 70 ns cs fall to dout enable t dv c load = 50pf 80 ns cs rise to dout disable t tr c load = 50pf 80 ns cs to sclk rise setup t css 100 ns cs to sclk rise hold t csh 0 ns sclk high pulse width t ch 80 ns sclk low pulse width t cl 80 ns sclk fall to sstrb t sstrb c load = 50pf 80 ns cs fall to sstrb enable t sdv c load = 50pf, external clock mode 80 ns cs rise to sstrb disable t str c load = 50pf, external clock mode 80 ns sstrb rise to sclk rise t sck internal clock mode 0 ns rst pulse width t rs 208 ns
max1142/MAX1143 14-bit adc, 200ksps, +5v single-supply with refer ence 6 _______________________________________________________________________________________ t ypical operating characteristics (max1142/MAX1143, av dd = dv dd = +5v , f sclk = 4.8mhz, external clock (50% duty cycle), 24-clocks/conversion (200ksps), bipo - lar input, external ref = +4.096v, 0.22 f bypassing on refadj, 2.2 f on ref, 1 f on cref, t a = 25 c, unless otherwise noted.) -1.0 -0.6 -0.8 -0.2 -0.4 0.2 0 0.4 0.8 0.6 1.0 1 3433 5149 6865 1717 8581 10297 12013 13729 15445 integral nonlinearity vs. digital output code max1142 toc01 digital output code integral nonlinearity (lsb) -1.0 -0.5 0.5 0 1.0 1 3263 4894 6525 8156 1632 9787 11418 13049 14680 1631 differential nonlinearity vs. digital output code max1142 toc02 digital output code differential nonlinearity (lsb) 9.5 10.1 9.9 9.7 10.5 10.3 11.3 11.1 10.9 10.7 11.5 -40 -20 0 20 40 60 80 total supply current vs. temperature max1142/3 toc03 temperature ( c) total supply current (ma) a: avdd, dvdd = +4.75v b: avdd, dvdd = +5.00v c: avdd, dvdd = +5.25v c b a -4 0 -1 -2 -3 offset voltage vs. temperature max1142/3 toc04 temperature ( c) offset voltage (v) -40 20 40 -20 0 60 80 a: av dd , dv dd = +4.75v b: av dd , dv dd = +5.00v c: av dd , dv dd = +5.25v a b c gain error vs. temperature max1142/3 toc05 gain error (% full scale) 0 0.04 0.03 0.02 0.01 temperature ( c) -40 20 40 -20 0 60 80 a: av dd , dv dd = +4.75v b: av dd , dv dd = +5.00v c: av dd , dv dd = +5.25v a b c 0.01 0.1 1 10 100 total supply current vs. conversion rate (using shutdown) max1142/3 toc06 conversion rate (ksps) total supply current (ma) 0 100 1000 1 10
max1142/MAX1143 14-bit adc, 200ksps, +5v single-supply with refer ence _______________________________________________________________________________________ 7 0 20 10 30 40 60 50 90 80 70 100 110 120 0.1 1 10 100 sfdr plot max1142/3 toc10 frequency (khz) amplitude (db) f sample = 200khz max1142/3 toc11 0 -20 -10 -30 -40 -60 -50 -90 -80 -70 -100 -110 0.1 1 10 100 thd plot frequency (khz) amplitude (db) f sample = 200khz t ypical operating characteristics (continued) (max1142/MAX1143, av dd = dv dd = +5v , f sclk = 4.8mhz, external clock (50% duty cycle), 24-clocks/conversion (200ksps), bipo - lar input, external ref = +4.096v, 0.22 f bypassing on refadj, 2.2 f on ref, 1 f on cref, t a = 25 c, unless otherwise noted.) 1.010 1.005 1 0.995 0.990 -40 40 0 60 -20 20 80 normalized ref voltage vs. temperature max1142/3 toc07 temperature ( c) normalized ref voltage -120 -110 -80 -40 -60 -20 0 0 18 9 27 36 45 54 63 72 81 90 99 fft plot max1142/3 toc08 frequency (khz) amplitude (db) f sample = 200khz f in = 5khz max1142/3 toc09 0 20 10 30 40 60 50 90 80 70 100 0.1 1 10 100 sinad plot frequency (khz) amplitude (db) f sample = 200khz
max1142/MAX1143 14-bit adc, 200ksps, +5v single-supply with refer ence 8 _______________________________________________________________________________________ pin name function 1 ref reference buffer output/adc reference input. reference voltage for analog-to-digital conversion. in internal reference mode, the reference buffer provides a +4.096v nominal output, externally adjustable at refadj. in external reference mode, disable the internal buffer by pulling refadj to av dd . bypass to agnd with a 2.2f capacitor when using the internal reference. 2 refadj bandgap reference output/ bandgap reference buffer input. bypass to agnd with 0.22f. when using an external reference , connect refadj to av dd to disable the internal bandgap reference. 3 agnd analog ground. this is the primary analog ground (star ground). 4 av dd analog supply 5v 5%. bypass av dd to agnd (pin 3) with a 0.1f capacitor. 5 dgnd digital ground 6 shdn shutdown control input. drive shdn low to put the adc in shutdown mode. 7 p2 user-programmable output 2 8 p1 user-programmable output 1 9 p0 user-programmable output 0 10 sstrb serial strobe output. in internal clock mode, sstrb goes low when the adc begins a conversion and goes high when the conversion is finished. in external clock mode, sstrb pulses high for one clock period before the msb decision. it is high impedance when cs is high in external clock mode. 11 dout serial data output. msb first, straight binary format for unipolar input, twos complement for bipolar input. each bit is clocked out of dout at the falling edge of sclk. 12 rst r e s e t i n p u t . d r i v e r s t l o w t o p u t t h e d e v i c e i n t h e p o w e r - o n d e f a u l t m o d e . s e e t h e p o w e r - o n r e s e t s e c t i o n . 13 sclk serial data clock input. serial data on din is loaded on the rising edge of sclk, and serial data is updated on dout on the falling edge of sclk. in external clock mode, sclk sets the conversion speed. 14 dgnd digital ground. connect to pin 5. 15 dv dd digital supply 5v 5%. bypass dv dd to dgnd (pin 14) with a 0.1f capacitor. 16 din serial data input. serial data on din is latched on the rising edge of sclk. 17 cs chip select input. drive cs low to enable the serial interface. when cs is high, dout is high-impedance. in external clock mode sstrb is high-impedance when cs is high. 18 cref reference buffer bypass. bypass cref to agnd (pin 3) with 1f. 19 agnd analog ground. connect pin 19 to pin 3. 20 ain analog input pin description
max1142/MAX1143 14-bit adc, 200ksps, +5v single-supply with refer ence _______________________________________________________________________________________ 9 detailed description the max1142/MAX1143 analog-to-digital converters (adcs) use a successive-approximation technique and input track/hold (t/h) circuitry to convert an analog signal to a 14-bit digital output. the max1142/MAX1143 easily interfaces to microprocessors ( ps). the data bits can be read either during the conversion in external clock mode or after the conversion in internal clock mode. in addition to a 14-bit adc, the max1142/MAX1143 include an input scaler, an internal digital microcontroller, calibration circuitry, an internal clock generator, and an internal bandgap reference. the input scaler for the max1142 enables conversion of input signals ranging from 0 to +12v (unipolar input) or 12v (bipolar input). the MAX1143 accepts 0 to +4.096v (unipolar input) or 4.096v (bipolar input). input range selection is software controlled. calibration to minimize linearity, offset, and gain errors, the max1142/MAX1143 have on-demand software calibra - tion. initiate calibration by writing a control-byte with bit m1 = 0, and bit m0 = 1 (see table 1). select internal or external clock for calibration by setting the int/ ext bit in the control-byte. calibrate the max1142/MAX1143 with the clock used for performing conversions. offsets resulting from synchronous noise (such as the conversion clock) are canceled by the max1142/ MAX1143s calibration circuitry. however, because the magnitude of the offset produced by a synchronous sig - nal depends on the signals shape, recalibration may be appropriate if the shape or relative timing of the clock or other digital signals change, as might occur if more than one clock signal or frequency is used. input scaler the max1142/MAX1143 have an input scaler which allows conversion of true bipolar input voltages while operating from a single +5v supply. the input scaler attenuates and shifts the input, as necessary, to map the external input range to the input range of the internal dac. the max1142 analog input range is 0 to +12v (unipolar) or 12v (bipolar). the MAX1143 analog input range is 0 to +4.096v (unipolar) or 4.096v (bipolar). unipolar and bipolar mode selection is configured with bit 6 of the serial control-byte. figure 1 shows the equivalent input circuit of the max1142/MAX1143. the resistor network on the analog input provides 16.5v fault protection. this circuit limits the current going into or out of the pin, to less than 2ma. the overvoltage protection is active, even if the device is in a power-down mode, or if av dd = 0. digital interface the digital interface pins consist of shdn , rst , sstrb, dout, sclk, din and cs . bringing shdn low, places the max1142/MAX1143 in its 2.5 a shutdown mode. a logic low on rst halts the max1142/MAX1143 opera - tion and returns the part to its power-on reset state. in external clock mode, sstrb is low and pulses high for one clock cycle at the start of conversion. in internal clock mode sstrb goes low at the start of the conver - sion, and goes high to indicate the conversion is fin - ished. the din input accepts control-byte data which is clocked in on each rising edge of sclk. after cs goes low or after a conversion or calibration completes, the first logic 1 clocked-into din is interpreted as the start bit, the msb of the 8-bit control-byte. the sclk input is the serial data transfer clock which clocks data in and out of the max1142/MAX1143. sclk also drives the a/d conversion steps in external clock mode (see internal and external clock modes section). dout is the serial output of the conversion result. dout is updated on the falling edge of sclk. dout is high-impedance when cs is high. cs must be low for the max1142/MAX1143 to accept a control-byte. the serial interface is disabled when cs is high. s1 = bipolar/unipolar s2, s3 = t/h switch s3 s2 ain s1 r1 2.5k w r3 r2 vol t age reference t/h out hold hold track track bipolar unipolar r2 = 7.6k w (max1142) or 2.5k w (MAX1143) r3 = 3.9k w (max1142) or infinity (MAX1143) c hold 30pf figure 1. equivalent input circuit
max1142/MAX1143 14-bit adc, 200ksps, +5v single-supply with refer ence 10 ______________________________________________________________________________________ user-programmable outputs the max1142/MAX1143 have three user-programma - ble outputs: p0, p1 and p2. the power-on default state for the programmable outputs is zero. these are push- pull cmos outputs suitable for driving a multiplexer, a pga, or other signal preconditioning circuitry. the user- programmable outputs are controlled by bits 0, 1 and 2 of the control-byte (table 2). the user-programmable outputs are set to zero during power-on reset (por) or when rst goes low. during hardware or software shutdown p0, p1, and p2 are unchanged and remain low-impedance. starting a conversion start a conversion by clocking a control-byte into the devices internal shift register. with cs low, each rising edge on sclk clocks a bit from din into the max1142/MAX1143s internal shift register. after cs goes low or after a conversion or calibration completes, the first arriving logic 1 is defined as the start bit of the control-byte. until this first start bit arrives, any number of logic 0 bits can be clocked into din with no effect. if at any time during acquisition or conversion, cs is brought high and then low again, the part is placed into a state where it can recognize a new start bit. if a new start bit occurs before the current conver - sion is complete, the conversion is aborted and a new acquisition is initiated. table 1 shows the control-byte format. internal and external clock modes the max1142/MAX1143 may use either the external serial clock or the internal clock to perform the succes - sive-approximation conversion. in both clock modes, the external clock shifts data in and out of the max1142/MAX1143. bit 5 (int/ ext ) of the control-byte programs the clock mode. external clock in external clock mode, the external clock not only shifts data in and out, but it also drives the a/d conver - sion steps. in short acquisition mode, sstrb pulses high for one clock period after the seventh falling edge of sclk, following the start bit. the msb of the conver - sion is available at dout on the eighth falling edge of sclk (figure 2). in long acquisition mode, when using the external clock, sstrb pulses high for one clock period after the fifteenth falling edge of sclk, following the start bit. the msb of the conversion is available at dout on the sixteenth falling edge of sclk (figure 3). table 1. control-byte format bit7 (msb) bit6 bit5 bit4 bit3 bit2 bit1 bit0 (lsb) start uni/ bip int/ ext m1 m0 p2 p1 p0 bit name description 7 (msb) start the first logic 1 bit, after cs goes low, defines the beginning of the control-byte 6 uni/ bip 1 = unipolar, 0 = bipolar. selects unipolar or bipolar conversion mode. in unipolar mode, analog input signals from 0 to +12v (max1142) or 0 to v ref (MAX1143) can be converted. in bipolar mode analog input signals from -12v to +12v (max1142) or -v ref to +v ref (MAX1143) can be converted. 5 int/ ext selects the internal or external conversion clock. 1 = internal, 0 = external. 4 m1 m1 m0 mode 0 0 24 external clocks per conversion (short acquisition mode) 0 1 start calibration. starts internal calibration 1 0 software power-down mode 3 m0 1 1 32 external clocks per conversion (long acquisition mode) 2 1 0(lsb) p2 p1 p0 these three bits are stored in a port register and output to pins p2Cp0 for use in addressing a mux or pga. these three bits are updated in the port register simultaneously when a new control-byte is written.
max1142/MAX1143 14-bit adc, 200ksps, +5v single-supply with refer ence ______________________________________________________________________________________ 11 in external clock mode, sstrb is high-impedance when cs is high. in external clock mode, cs is normally held low during the entire conversion. if cs goes high during the conversion, sclk is ignored until cs goes low. this allows external clock mode to be used with 8- bit bytes. internal clock in internal clock mode, the max1142/MAX1143 gener - ates its own conversion clock. this frees the micro - processor from the burden of running the sar conver- sion clock, and allows the conversion results to be read back at the processors convenience, at any clock rate up to 8mhz. sstrb goes low at the start of the conversion and goes high when the conversion is complete. sstrb will be low for a maximum of 6 s, during which time sclk should remain low for best noise performance. an inter - nal register stores data when the conversion is in progress. sclk clocks the data out of the internal stor - age register at any time after the conversion is com - plete. the msb of the conversion is available at dout when sstrb goes high. the subsequent 15 falling edges on sclk shift the remaining bits out of the internal storage register (figure 4). cs does not need to be held low once a conversion is started. when internal clock mode is selected, sstrb does not go into a high-impedance state when cs goes high. figure 5 shows the sstrb timing in internal clock mode. in internal clock mode, data can be shifted into the max1142/MAX1143 at clock rates up to 4.8mhz, provided that the minimum acquisition time, t acq , is kept above 1.14 s in bipolar mode and 1.82 s in unipolar-mode. data can be clocked out at 8mhz. output data the output data format is straight binary for unipolar conversions and twos complement in bipolar mode. in both modes the msb is shifted out of the max1142/ MAX1143 first. table 2. user-programmable outputs output pin programmed through control- byte power-on or rst default description p2 bit 2 0 p1 bit 1 0 p0 bit 0 0 u s e r p r o g r a m m a b l e o u t p u t s f o l l o w t h e s t a t e o f t h e c o n t r o l - b y t e s t h r e e l s b s , a n d a r e u p d a t e d s i m u l t a n e o u s l y w h e n a n e w c o n t r o l - b y t e i s w r i t t e n . o u t p u t s a r e p u s h - p u l l . i n h a r d w a r e a n d s o f t w a r e s h u t d o w n , t h e s e o u t p u t s a r e u n c h a n g e d a n d r e m a i n l o w - i m p e d a n c e . acquisition conversion idle idle sclk dout a/d st a te din sstrb cs 4 1 8 12 st ar t m1 m0 p2 p1 p0 uni/ bip int/ ext 15 21 24 b10 b9 b12 b11 b8 b7 b2 b13 msb b0 lsb filled with zeros b1 x x t acq figure 2. short acquisition mode (24-clock cycles) external clock, bipolar mode
max1142/MAX1143 14-bit adc, 200ksps, +5v single-supply with refer ence 12 ______________________________________________________________________________________ sclk dout a/d st a te din sstrb cs 4 1 8 19 st ar t m1 m0 p2 p1 p0 uni/ bip int/ ext 15 21 32 b2 b12 b13 msb b11 b1 x x b0 lsb filled with zeros t acq acquisition conversion idle idle figure 3. long acquisition mode (32-clock cycles) external clock, bipolar mode s c l k d o u t d i n s s t r b c s 4 1 8 s t a r t m 1 m 0 p 2 p 1 p 0 u n i / b i p i n t / e x t 9 2 1 1 0 2 4 b 2 b 1 2 b 1 1 b 1 3 m s b b 1 x x b 0 l s b f i l l e d w i t h z e r o s t a c q t c o n v figure 4. internal clock mode timing, short acquisition, bipolar mode po clocked in t sstrb t conv t sck t css sstrb sclk note: for best noise performance, keep sclk low during conversion. t csh cs figure 5. internal clock mode sstrb detailed timing
max1142/MAX1143 14-bit adc, 200ksps, +5v single-supply with refer ence ______________________________________________________________________________________ 13 data framing the falling edge of cs does not start a conversion on the max1142/MAX1143. the first logic high clocked into din is interpreted as a start bit and defines the first bit of the control-byte. a conversion starts on the falling edge of sclk, after the seventh bit of the control-byte (the p1 bit) is clocked into din. the start bit is defined as: the first high bit clocked into din with cs low, any - time the converter is idle, e.g. after av dd is applied, or as the first high bit clocked into din after cs is pulsed high, then low. or if a falling edge on cs forces a start bit before the conversion or calibration is complete, then the cur - rent operation will be terminated and a new one started. applications infor mation power-on reset when power is first applied to the max1142/MAX1143 or if rst is pulsed low, the internal calibration registers are set to their default values. the user-programmable registers (p0, p1 and p2) are low, and the device is configured for bipolar mode with internal clocking. calibration to compensate the max1142/MAX1143 for tempera - ture drift and other variations, they should be periodi - cally calibrated. after any change in ambient temperature more than 10 c, the device should be recalibrated. a 100mv change in supply voltage or any change in the reference voltage should be followed by a calibration. calibration corrects for errors in gain, off - set, integral nonlinearity and differential nonlinearity. the max1142/MAX1143 should be calibrated after power-up or the assertion of reset. make sure the power supplies and the reference voltage have fully settled prior to initiating the calibration sequence. initiate calibration by setting m1 = 0 and m0 = 1 in the control-byte. in internal clock mode, sstrb goes low at the beginning of calibration and goes high to signal the end of calibration, approximately 80,000 clock cycles later. in external clock mode, sstrb goes high at the beginning of calibration and goes low to signal the end of calibration. calibration should be performed in the same clock mode as will be used for conversions (figure 6). reference the max1142/MAX1143 can be used with an internal or external reference. an external reference can be con - nected directly at the ref pin or at the refadj pin. cref is an internal reference node and must be bypassed with a 1 f capacitor when using either the internal or an external reference. internal reference when using the max1142/MAX1143s internal refer - ence, place a 0.22 f ceramic capacitor from refadj to agnd and place a 2.2 f capacitor from ref to agnd. fine adjustments can be made to the internal reference voltage by sinking or sourcing current at refadj. the input impedance of refadj is nominally 9k . the internal reference voltage is adjustable to 1.5% with the circuit of figure 7. t sdv t sstrb t sstrb t str p1 clocked in sstrb sclk cs figure 6. external clock mode sstrb detailed timing
max1142/MAX1143 14-bit adc, 200ksps, +5v single-supply with refer ence 14 ______________________________________________________________________________________ external reference an external reference can be placed at either the input (refadj) or the output (ref) of the max1142/ MAX1143s internal buffer amplifier. when connecting an external reference to refadj, the input impedance is typically 9k . using the buffered refadj input makes buffering of the external reference unnecessary. the internal buffer output must be bypassed at ref with a 2.2 f capacitor. when connecting an external reference at ref, refadj must be connected to av dd . the input imped - ance at ref is 16k for dc currents. during conver - sion, an external reference at ref must deliver 250 a dc load current and have an output impedance of 10 or less. if the reference has a higher output impedance or is noisy, bypass it at the ref pin with a 4.7 f capac - itor. analog input the max1142/MAX1143 use a capacitive dac that provides an inherent track/hold function. drive ain with a source impedance less than 10 . any signal condi - tioning circuitry must settle with 16-bit accuracy in less than 500ns. limit the input bandwidth to less than half the sampling frequency to eliminate aliasing. the max1142/MAX1143 has a complex input impedance which varies from unipolar to bipolar mode (figure 1). input range the analog input range in unipolar mode is 0 to +12v for the max1142, and 0 to +4.096v for the MAX1143. in bipolar mode, the analog input can be -12v to +12v for the max1142, and -4.096v to +4.096v for the MAX1143. unipolar and bipolar mode is programmed with the uni/ bip bit of the control-byte. when using a reference other than the max1142/MAX1143s internal +4.096v reference, the full-scale input range will vary accordingly. the full-scale input range depends on the voltage at ref and the sampling mode selected (tables 3 and 4). input acquisition and settling clocking-in a control-byte starts input acquisition. in bipolar mode, the main capacitor array starts acquiring the input as soon as a start bit is recognized. if unipolar mode is selected by the second din bit, the part will immediately switch to unipolar sampling mode and acquire a sample. acquisition can be extended by eight clock cycles by setting m1 = 1, m0 = 1 (long acquisition mode). the sampling instant in short acquisition completes on the falling edge of the sixth clock cycle after the start bit (figure 2). +5v 510k w 100k w 24k w 0.22 f refadj max1142 figure 7. max1142 reference-adjust circuit table 3. unipolar full scale and zero scale part reference zero scale full scale internal 0 +12v max1142 external 0 +12(v ref /4.096) internal 0 +4.096v MAX1143 external 0 +v ref table 4. bipolar full scale, zero scale, and negative scale part reference negative full scale zero scale full scale internal -12v 0 +12v max1142 external -12(v ref /4.096) 0 +12(v ref /4.096) internal -4.096v 0 +4.096v MAX1143 external -v ref 0 +v ref
max1142/MAX1143 14-bit adc, 200ksps, +5v single-supply with refer ence ______________________________________________________________________________________ 15 acquisition is 5.5 clock cycles in short acquisition mode and 13.5 clock cycles in long acquisition mode. short acquisition mode is 24 clock cycles per conver - sion. using the external clock to run the conversion process limits unipolar conversion speed to 125ksps instead of 200ksps in bipolar mode. the input resis - tance in unipolar mode is larger than that of bipolar mode (figure1). the rc time constant in unipolar mode is larger than that of bipolar mode, reducing the maxi - mum conversion rate in 24 external clock mode. long acquisition mode with external clock allows both unipo - lar and bipolar sampling of 150ksps (4.8mhz/32 clock cycles) by adding eight extra clock cycles to the con - version. most applications require an input buffer amplifier. if the input signal is multiplexed, the input channel should be switched immediately after acquision, rather than near the end of or after a conversion. this allows more time for the input buffer amplifier to respond to a large step change in input signal. the input amplifier must have a high enough slew-rate to complete the required output voltage change before the beginning of the acquisition time. at the beginning of acquisition, the capacitive dac is connected to the amplifier output, causing some output disturbance. ensure that the sam - pled voltage has settled to within the required limits before the end of the acquisition time. if the frequency of interest is low, ain can be bypassed with a large enough capacitor to charge the capacitive dac with very little change in voltage. however, for ac use, ain must be driven by a wideband buffer (at least 10mhz), which must be stable with the dacs capacitive load (in parallel with any ain bypass capacitor used) and also settle quickly (figures 8 or 9). digital noise digital noise can couple to ain and ref. the conver - sion clock (sclk) and other digital signals that are active during input acquisition, contribute noise to the conversion result. if the noise signal is synchronous to the sampling interval, an effective input offset is pro - duced. asynchronous signals produce random noise on the input, whose high-frequency components may be aliased into the frequency band of interest. minimize noise by presenting a low impedance (at the frequen - cies contained in the noise signal) at the inputs. this requires bypassing ain to agnd, or buffering the input with an amplifier that has a small-signal bandwidth of several mhz, or preferably both. ain has a bandwidth of about 4mhz. 4 7 6 2 3 in +15v -15v 0.0033 m f 0.1 m f 0.1 m f 1k w 20 w ain max427 1000pf figure 8. ain buffer for ac/dc use 4 7 6 2 3 in +5v -5v ain 0.1 m f 0.1 m f 0.1 m f 22 w 510 w max410 figure 9. 5v buffer for ac/dc use has 3.5v swing
max1142/MAX1143 14-bit adc, 200ksps, +5v single-supply with refer ence 16 ______________________________________________________________________________________ offsets resulting from synchronous noise (such as the conversion clock) are canceled by the max1142/ MAX1143s calibration scheme. the magnitude of the offset produced by a synchronous signal depends on the signals shape. recalibration may be appropriate if the shape or relative timing of the clock or other digital signals change, as might occur if more than one clock signal or frequency is used. distortion avoid degrading dynamic performance by choosing an amplifier with distortion much less than the max1142/ MAX1143s thd (-88db) at frequencies of interest. if the chosen amplifier has insufficient common-mode rejection, which results in degraded thd performance, use the inverting configuration to eliminate errors from common-mode voltage. low temperature-coefficient resistors reduce linearity errors caused by resistance changes due to self-heating. to reduce linearity errors due to finite amplifier gain, use an amplifier circuit with sufficient loop gain at the frequencies of interest. dc accuracy if dc accuracy is important, choose a buffer with an offset much less than the max1142/MAX1143s maxi - mum offset ( 6mv), or whose offset can be trimmed while maintaining good stability over the required tem - perature range. operating modes and serial interfaces the max1142/MAX1143 are fully compatible with microwire and spi/qspi devices. microwire and spi/qspi both transmit a byte and receive a byte at the same time. the simple software interface requires only three 8-bit transfers to perform a conversion, one 8-bit transfer to configure the adc, and two more 8-bit trans - fers to clock out the 14-bit conversion result. mode 1 short acquisition mode (24 sclk) configure short acquisition by setting m1 = 0 and m0 = 0. in short acquisition mode, the acquisition time is 5.5 clock cycles. the total period is 24-clock cycles per conversion. mode 2 long acquisition mode (32 sclk) configure long acquisition by setting m1 = 1 and m0 = 1. in long acquisition mode, the acquisition time is 13.5 clock cycles. the total period is 32 clock cycles per conversion. calibration mode a calibration is initiated through the serial interface by setting m1 = 0, m0 = 1. calibration can be done in either internal or external clock mode, though it is desir - able that the part be calibrated in the same mode in which it will be used to do conversions. the part will remain in calibration mode for approximately 80,000 clock cycles, unless the calibration is aborted. calibration is halted if rst or shdn goes low, or if a valid start condition occurs. software shut-down a software power-down is initiated by setting m1 = 1, m0 = 0. after the conversion completes, the part shuts down. it reawakens upon receiving a new start bit. conversions initiated with m1 = 1 and m0 = 0 (shut - down) use the acquisition mode selected for the previ - ous conversion. shutdown mode the max1142/MAX1143 may be shut down by pulling shdn low or by asserting software shutdown. in addi - tion to lowering power dissipation to 13 w, consider - able power can be saved by shutting down the converter for short periods between conversions. duration will be affected by ref startup time with inter - nal reference. there is no need to perform a calibration after the converter has been shut down, unless the time in shutdown is long enough that the supply voltage or ambient temperature may have changed. supplies, layout, grounding and bypassing for best system performance, use separate analog and digital ground planes. the two ground planes should be tied together at the max1142/MAX1143. use pins 3 and 14 as the primary agnd and dgnd, respectively. if the analog and digital supplies come from the same source, isolate the digital supply from the analog with a low value resistor (10 ). the max1142/MAX1143 are not sensitive to the order of av dd and dv dd sequencing. either supply can be present in the absence of the other. do not apply an external reference voltage until after both av dd and dv dd are present. be sure that digital return currents do not pass through the analog ground. all return current paths must be low-impedance. a 5ma current flowing through a pc board ground trace impedance of only 0.05 , creates an error voltage of about 250 v, or about 2lsbs error with a 4v full-scale system. the board layout should ensure that the digital and analog signal lines are kept separate. do not run analog and digital lines parallel to one another. if you must cross one with the other, do so at right angles. the adc is sensitive to high-frequency noise on the av dd power supply. bypass this supply to the analog ground plane with 0.1 f. if the main supply is not ade -
max1142/MAX1143 14-bit adc, 200ksps, +5v single-supply with refer ence ___________________________________________________ 17 quately bypassed, add an additional 1 f or 10 f low- esr capacitor in parallel with the primary bypass capacitor. transfer function figures 10 and 11 show the max1142/MAX1143s transfer functions. in unipolar mode, the output data is in binary format and in bipolar mode, it is twos comple - ment format. definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight-line can be either a best straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. inl for the max1142/MAX1143 is measured using the end- point method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the time between the samples. aperture delay aperture delay (t ad ) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. signal-to-noise ratio for a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (snr) is the ratio of full- scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical, minimum analog-to-digital noise is caused by quantization error only and results directly from the adcs resolution (n-bits): snr = (6.02 5 n + 1.76)db in reality, there are other noise sources besides quanti - zation noise, including thermal noise, reference noise, clock jitter, etc. therefore, snr is calculated by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamen - tal, the first five harmonics and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequencys rms amplitude to the rms equivalent of all other adc output signals: sinad (db) = 20 5 log (signal rms /noise rms ) output code full-scale transition 11 . . . 111 11 . . . 110 11 . . . 101 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 12 3 0 fs fs - 3/2lsb fs = +4.096v 1lsb = fs 16384 input voltage (lsbs) figure 10. MAX1143 unipolar transfer function, 4.096v = full- scale 011 . . . 111 011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 -fs 0v input voltage (lsbs) +fs - 1lsb 1lsb = 8.192 16384 +fs = +4.096v -fs = -4.096v output code figure 11. MAX1143 bipolar transfer function, 4.096v = full- scale
effective number of bits effective number of bits (enob) indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adcs error consists of quanti - zation noise only. with an input range equal to the full- scale range of the adc, calculate the effective number of bits as follows: enob = (sinad - 1.76) / 6.02 total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of rms amplitude of the fundamental (maximum signal compo - nent), to the rms value of the next largest distortion component. chip infor mation transistor count: 21,807 process : bicmos thd = + + + ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 log / v v v v v max1142/MAX1143 14-bit adc, 200ksps, +5v single-supply with refer ence 18 ______________________________________________________________________________________ or dering infor mation (continued) part temp. range pin- package inl (lsb) max1142aeap -40 c to +85 c 20 ssop 1 max1142beap -40 c to +85 c 20 ssop 2 MAX1143 acap* 0 c to +70 c 20 ssop 1 MAX1143bcap* 0 c to +70 c 20 ssop 2 MAX1143aeap* -40 c to +85 c 20 ssop 1 MAX1143beap* -40 c to +85 c 20 ssop 2 a v dd dv dd sclk sclk mosi miso i/o i/o din dout sstrb dgnd agnd ref adj ref ain to dgnd mc68hcxx 0.1 m f 0.22 m f 2.2 m f rst cs shdn max1142 MAX1143 0.1 m f +5v +5v 1 m f cref t ypical application cir cuit *future productcontact factory for availability.
max1142/MAX1143 14-bit adc, 200ksps, +5v single-supply with refer ence ______________________________________________________________________________________ 19 functional diagram cref av dd 9k w agnd refadj ref cs rst reference ain dv dd dgnd sclk din analog timing control input scaling network serial output port serial input port memory calibration engine clock generator control dac comparator p2 sstrb dout p1 p0 shdn max1142 MAX1143
max1142/MAX1143 14-bit adc, 200ksps, +5v single-supply with refer ence maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________ maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. package infor mation ssop.eps

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